Design of Self-Checking Discrete Devices Based on Boolean Signal Correction with Weighted Sum Codes in the Residue Ring of a Given Modulus

It is proposed to design concurrent error-detection (CED) circuits for discrete automation and computing devices using Boolean signal correction (BSC) with weighted sum codes. Within this approach, a CED circuit corrects signals from all outputs of an object under diagnosis and involves a particular subset of codewords of a preselected weighted sum code. An algorithm is developed for selecting codewords used to design a CED circuit based on BSC; this algorithm allows choosing the best variant to cover faults at the object’s outputs and ensures the self-checking property of the circuit. The features of organizing CED circuits based on the above method are shown.